The present invention generally pertains to the field of computer networking. More particularly, the present invention is related to interrupt generation by a peripheral component.
Computers have become an integral tool used in a wide variety of different applications, such as in finance and commercial transactions, computer-aided design and manufacturing, health-care, telecommunication, education, etc. Computers are finding new applications as a result of advances in hardware technology and rapid development in software technology. Furthermore, a computer system""s functionality is dramatically enhanced by coupling stand-alone computers together to form a computer network. In a computer network, users may readily exchange files, share information stored on a common database, pool resources, and communicate via e-mail and via video teleconferencing.
One popular type of computer network is known as a local area network (LAN). LANs connect multiple computers together such that the users of the computers can access the same information and share data. Typically, in order to be connected to a LAN, a general purpose computer requires an expansion board generally known as a network interface card (NIC). Essentially, the NIC works with the operating system and central processing unit (CPU) of the host computer to control the flow of information over the LAN. Some NICs may also be used to connect a computer to the Internet.
The NIC, like other hardware devices, requires a device driver which controls the physical functions of the NIC and coordinates data transfers between the NIC and the host operating system. An industry standard for interfacing between the device driver and the host operating system is known as the Network Device Interface Specification, or NDIS, which is developed by Microsoft Corporation of Redmond, Wash. The operating system layer implementing the NDIS interface is generally known as an NDIS wrapper. Functionally, the NDIS wrapper arbitrates the control of the device driver between various application programs and provides temporary storage for the data packets.
In one type of prior art system, in order for a NIC to communicate with or access the CPU, an interrupt must be generated. In such a prior art approach, hardware on the NIC generates an interrupt when the NIC has an event to be serviced. Each these aforementioned interrupts has substantial CPU overhead associated therewith. That is, every time an interrupt is generated, the CPU must: cease performing its current selected task; store relevant data, pointers, and the like; service the event(s) which triggered the interrupt; and return to the selected task. With the advent of high speed applications and environments such as, for example, Gigabit Ethernet or asynchronous transfer mode (ATM), data is being transferred from and arriving at the NIC at much higher rate. As a result, of the higher data transfer speeds, the generation of interrupts by the NIC becomes increasingly frequent. In fact, conventional hardware based interrupt generation schemes could result in the NIC almost continuously asserting interrupts to the CPU of the host computer. Under such circumstances, the overhead associated with servicing each interrupt triggering event becomes prohibitively excessive. That is, prior art interrupt generation approaches do not optimally minimize CPU utilization and overhead.
In an attempt to alleviate the problem of excessive CPU utilization and overhead due to frequent interrupt generation, one prior art approach employs interrupt coalescing. In such an approach, groups of events (e.g. transmit complete events, receive complete events, and the like) are stored or xe2x80x9ccoalesced,xe2x80x9d and a single interrupt is generated once a selected number of the events are obtained. That is, instead of generating an interrupt each time a transmit complete event occurs, an interrupt coalesced approach only generates an interrupt when, for example, five transmit complete events have been coalesced. In such an approach, CPU overhead associated with servicing transmit complete events is reduced. As an example, in order to service five transmit complete events in a non-coalesced approach, the CPU must cease performing its current selected task; store relevant data, pointers, and the like; service only a single transmit complete event; and return to the selected task on five separate occasions. However, to service five coalesced transmit complete events, the CPU will cease performing its current selected task; store relevant data, pointers, and the like; service all five coalesced transmit complete events; and return to the selected task on only one occasion. Although interrupt coalescing can reduce CPU utilization and overhead, interrupt coalescing alone is not sufficient to meet the needs of current peripheral components such as NICs. That is, even with interrupt coalescing, excessive CPU utilization and overhead problems still exist.
Thus, a need exists for a peripheral component interrupt generation system that reduces the frequency with which interrupts are generated. A need also exists for a peripheral component interrupt generation system which minimizes the CPU overhead associated with the servicing of interrupts. Still another need exists for a peripheral component interrupt generation system which meets the above-listed needs and which operates effectively in a coalesced interrupt environment.
The present invention provides a peripheral component interrupt generation system that reduces the frequency with which interrupts are generated. The present invention also provides a peripheral component interrupt generation system that minimizes the CPU overhead associated with the servicing of interrupts. The present invention further provides a peripheral component interrupt generation system which meets the above-listed needs and which operates effectively in a coalesced interrupt environment. The above accomplishments are achieved with a peripheral component interrupt generation system that optimizes interrupts in a coalesced interrupt environment.
Specifically, in one embodiment, the present invention, a peripheral component such as, for example, a network interface card stores coalesced peripheral component events. The peripheral component causes the generation of a first interrupt upon the occurrence of a selected quantity of peripheral component events (the xe2x80x9cquantity thresholdxe2x80x9d). In the present embodiment, a peripheral component driver such as, for example, a network interface card driver then services the peripheral component events that have been coalesced. The peripheral component driver is typically limited in the number of peripheral component events that the peripheral component driver can service at any one time. Thus, some of the peripheral component events will be serviced immediately, and others will not be serviced. The peripheral component events that have not yet been serviced will remain in memory storage until they are serviced. In one embodiment of the present invention, the peripheral component monitors the servicing of peripheral component events to determine the number of peripheral component events not serviced. The quantity threshold is adjusted according to the number of peripheral component events not serviced such that the next interrupt delivers an optimum number of peripheral component events. As a result, the present embodiment optimizes the frequency with which interrupts are generated and minimizes the CPU overhead associated with the servicing of interrupts.
In another embodiment, the present invention includes a peripheral component such as, for example, a network interface card that stores coalesced peripheral component events and that determines the time interval between succeeding peripheral component events. The peripheral component causes the generation of an interrupt when the time interval between succeeding peripheral component events is greater than a predetermined threshold (the xe2x80x9ctime thresholdxe2x80x9d). The predetermined threshold is set so as to cause the generation of an interrupt at an idle time period. As a result, the present embodiment generates interrupts at idle time periods, optimizing the frequency with which interrupts are generated and minimizing the CPU overhead associated with the servicing of interrupts.
In yet another embodiment, the present invention includes a peripheral component such as, for example, a network interface card that stores coalesced peripheral component events and that determines the storage time for coalesced peripheral component events. The peripheral component causes the generation of an interrupt when the storage time for a coalesced peripheral component event is greater than a predetermined threshold (the xe2x80x9cstorage time thresholdxe2x80x9d). The storage time threshold is set so as to cause the generation of an interrupt in a timely manner, assuring that coalesced interrupts are not stored for too long of a time. As a result, the present embodiment optimizes the frequency with which interrupts are generated and minimizes the CPU overhead associated with the servicing of interrupts.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.